View MAX793_5231639.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

_______________general description the MAX793/max794/max795 microprocessor (?) supervisory circuits monitor and control the activities of +3.0v/+3.3v ?s by providing backup-battery switchover, among other features such as low-line indication, ? reset, write protection for cmos ram, and a watchdog (see the selector guide below). the backup-battery volt- age can exceed v cc , permitting the use of 3.6v lithium batteries in systems using 3.0v to 3.3v for v cc . the MAX793/max795 offer a choice of reset threshold voltage range (denoted by suffix letter): 3.00v to 3.15v (t), 2.85v to 3.00v (s), and 2.55v to 2.70v (r). the max794? reset threshold is set externally with a resistor divider. the MAX793/max794 are available in 16-pin dip and narrow so packages, and the max795 comes in 8-pin dip and so packages. ________________________applications battery-powered computers and controllers embedded controllers intelligent controllers critical ? power monitoring portable equipment ____________________________features MAX793/max794/max795 precision supply-voltage monitor: fixed reset trip voltage (MAX793/max795) adjustable reset trip voltage (max794) guaranteed reset assertion to v cc = 1v backup-battery power switching?attery voltage can exceed v cc on-board gating of chip-enable signals?ns max propagation delay MAX793/max794 only battery freshness seal battery ok output (MAX793) uncommitted voltage monitor for power-fail or low-battery warning independent watchdog timer (1.6s timeout) manual reset input ______________ordering information ordering information continued on last page. * the MAX793/max795 offer a choice of reset threshold voltage. select the letter corresponding to the desired reset threshold voltage range (t = 3.00v to 3.15v, s = 2.85v to 3.00v, r = 2.55v to 2.70v) and insert it into the blank to complete the part number. the max794? reset threshold is adjustable. MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits ________________________________________________________________ maxim integrated products 1 MAX793 reset lowline wdi ce in ce out 3.0v or 3.3v +5v batt a0-a15 mr +5v supply failure batt on pfi wdo out cmos ram address decoder 0.1 f pmos 0.1 f v cc pfo gnd i/o p nmi reset v cc v cc 0.1 f 3.6v batt ok (optional) si9433dy siliconix 19-0366; rev 3; 2/03 part* MAX793 _cpe MAX793_cse MAX793_epe -40? to +85? 0? to +70? 0? to +70? temp range pin-package 16 plastic dip 16 narrow so 16 plastic dip MAX793_ese -40? to +85? 16 narrow so feature active-low reset active-high reset programmable reset threshold low-line early warning output MAX793 ? ? ? max794 ? ? ? ? max795 ? backup-battery switchover external switch driver power-fail comparator ? ? ? ? ? ? battery ok output ? ? ? _____________________selector guide __________typical operating circuit watchdog input battery freshness seal ? ? ? ? manual reset input ? ? ? chip-enable gating ? ? pins-package 16-dip/so 16-dip/so 8-dip/so pin configurations appear at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
? MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = 3.17v to 5.5v for the MAX793t/max795t, v cc = 3.02v to 5.5v for the MAX793s/max795s, v cc = 2.72v to 5.5v for the MAX793r/max794/max795r, v batt = 3.6v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. terminal voltage (with respect to gnd) v cc ........................................................................-0.3v to 6.0v v batt .....................................................................-0.3v to 6.0v all other inputs ..................-0.3v to the higher of v cc or v batt continuous input current v cc .................................................................................200ma v batt ................................................................................50ma gnd ..................................................................................20ma output current v out ................................................................................200ma all other outputs ..............................................................20ma continuous power dissipation (t a = +70?) 8-pin plastic dip (derate 9.09mw/? above +70?) .....727mw 8-pin so (derate 5.88mw/? above +70?)..................471mw 16-pin plastic dip (derate 10.53mw/? above +70?) .842mw 16-pin narrow so (derate 9.52mw/? above +70?) ...696mw operating temperature ranges MAX793_c_ _/max794c_ _/max795_c_ _ ......... 0? to +70? MAX793_e_ _/max794e_ _/max795_e_ _ ........-40? to +85? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? max79_e max79_c v batt > v cc (note 6) i out = 250? (note 4) i out = 30ma (note 4) v sw > v cc > 1.75v (note 5) i out = 75ma v batt = 2.3v conditions battery switch threshold (v cc falling) v 2.30 2.41 2.52 v sw 2.55 2.68 2.80 2.69 2.82 2.95 mv 20 65 v cc - v batt v v batt - 0.14 v out out output voltage in battery-backup mode v batt - 0.1 v batt - 0.034 v 1.1 5.5 1.0 5.5 operating voltage range, v cc , v batt (note 1) v v cc - 0.001 v cc - 0.5mv v out out output voltage in normal mode v cc - 0.12 v cc - 0.050 v cc - 0.3 v cc - 0.125 ? 0.5 battery leakage current (note 3) ? 1 batt supply current (excluding i out ) (note 2) units min typ max symbol parameter v cc = 0v, v out = 0v ? 1 batt leakage current, freshness seal enabled i out = 250? i out = 1ma MAX793t/max795t MAX793s/max795s this value is identical to the reset threshold, v cc rising for v batt > v rst v cc - v batt MAX793r/max795r/ max794 v batt < v rst mv 25 65 battery switch threshold (v cc rising) (note 7) MAX793/max794, mr = v cc ? 62 80 i supply 46 60 v cc supply current (excluding i out , i ce out ) v cc = 2.1v, v batt = 2.3v ? 32 45 i supply v cc supply current in battery-backup mode (excluding i out ) v cc < 3.6v v cc < 5.5v MAX793/max794 max795 24 35 max795 49 70 35 50 v cc < 3.6v v cc < 5.5v
MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = 3.17v to 5.5v for the MAX793t/max795t, v cc = 3.02v to 5.5v for the MAX793s/max795s, v cc = 2.72v to 5.5v for the MAX793r/max794/max795r, v batt = 3.6v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) conditions 2.85 2.925 3.00 3.00 3.075 3.15 units min typ max symbol parameter v cc falling 3.00 3.085 3.17 2.55 2.625 2.70 v rst v v rst in v v cc falling v cc rising reset in threshold (max794 only) 1.212 1.240 1.262 reset threshold (note 8) 2.55 2.635 2.72 2.85 2.935 3.02 v lr mv MAX793 lowline -to-reset threshold, (v lowline - v rst ), v cc falling v cc < 3.6v 51525 30 45 60 mv MAX793s/max795s MAX793t/max795t max794 MAX793 3.08 low-line comparator hysteresis 3.23 mv 10 10 ms t rp 140 200 280 reset timeout period v MAX793r/max795r 2.78 na v pfi rising v pfi falling pfi input current max794 v -25 2 25 v th 1.212 1.250 1.287 pfi input threshold 1.212 1.240 1.262 v ll 1.317 lowline threshold, v cc rising v v bok 2.00 2.25 2.50 batt ok threshold (MAX793) v oh v i source = 300?, v cc = v rst max batt ok, batt on, wdo , lowline output voltage high i source = 300?, v cc = v rst min 0.8v cc 0.86v cc v v oh 0.8v cc 0.86v cc reset output voltage high mv 10 20 pfi hysteresis, pfi rising MAX793t/max795t MAX793s/max795s MAX793r/max795r MAX793t/max795t MAX793s/max795s MAX793r/max795r na reset in leakage current (max794 only) -25 2 25 max794 v oh v i source = 65?, v cc = v rst max pfo output voltage high 0.8v cc v oh v i source = 100?, v cc = 2.3v, v batt = 3v batt on output voltage high 0.8v batt i leak ? v cc = v rst max reset output leakage current (note 9) -1 -1 i sc ? v cc = 3.3v, v pfo = 0v pfo output short to gnd current 180 500 v ol v i sink = 1.2ma; reset , lowline tested with v cc = v rst min; reset, battok, wdo tested with v cc = v rst max pfo , reset , reset, wdo , lowline output voltage low 0.08 0.2v cc input and output levels v cc rising 1.212 1.250 1.282
MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits 4 _______________________________________________________________________________________ conditions v ol v v ol v i sink = 3.2ma, v cc = v rst max max79_e, v batt = v cc = 1.2v, i sink = 200? batt on output voltage low max79_c, v batt = v cc = 1.0v, i sink = 40? 0.2v cc reset output voltage low units min typ max symbol parameter v il v t mr ns MAX793/max794 only v rst max < v cc < 5.5v mr pulse width 100 all inputs including pfo (note 10) 0.3v cc v ih 0.7v cc 0.17 0.3 0.13 0.3 electrical characteristics (continued) (v cc = 3.17v to 5.5v for the MAX793t/max795t, v cc = 3.02v to 5.5v for the MAX793s/max795s, v cc = 2.72v to 5.5v for the MAX793r/max794/max795r, v batt = 3.6v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) t md ns MAX793/max794 only, mr = 0v MAX793/max794 only ? mr -to-reset delay 25 70 250 mr pullup current 75 250 ? ns v cc = v rst max, figure 9 enable mode, v cc = v rst max ce in-to- ce out propagation delay disable mode 27 ce in-to- ce out resistance v oh v ol v v cc = v rst max, i out = 1.6ma, v ce in = 0v v cc = v rst max, i out = -1ma, v ce in = v cc ce out drive from ce in 0.2v cc 0.8v cc na 46 i leak ?0 ce in leakage current note 1: v cc supply current, logic input leakage, watchdog functionality (MAX793/max794), mr functionality (MAX793/max794), pfi functionality (MAX793/max794), and state of reset and reset (MAX793/max794) tested at v batt = 3.6v and v cc = 5.5v. the state of reset is tested at v cc = v cc min. note 2: tested at v batt = 3.6v, v cc = 3.5v and 0v. the battery current rises to 10? over a narrow transition window around v cc = 1.9v. note 3: leakage current into the battery is tested under the worst-case conditions at v cc = 5.5v, v batt = 1.8v and v cc = 1.5v, v batt = 1.0v. note 4: guaranteed by design. note 5: when v sw > v cc > v batt , out remains connected to v cc until v cc drops below v batt . the v cc -to-v batt comparator has a small 15mv typical hysteresis to prevent oscillation. for v cc < 1.75v (typical), out switches to batt regardless of v batt . note 6: when v batt > v cc > v sw , out remains connected to v cc until v cc drops below the battery switch threshold (v sw ). note 7: out switches from batt to v cc when v cc rises above the reset threshold, if v batt > v rst . in this case, switchover back to v cc occurs at the exact voltage that causes reset to be asserted, however, switchover occurs 200ms prior to reset. if v batt < v rst , out switches from batt to v cc when v cc exceeds v batt . note 8: the reset threshold tolerance is wider for v cc rising than for v cc falling to accommodate the 10mv typical hysteresis, which prevents internal oscillation. note 9: the leakage current into or out of the reset pin is tested with reset not asserted (reset output high impedance). note 10: pfo is normally an output, but is used as an input when activating the battery freshness seal. ? 10 reset to ce out high delay t wd sec 0v < v cc < 5.5v watchdog timeout period i oh = 500?, v cc < 2.3v ? 1.00 1.60 2.25 -1 0.01 1 wdi input current v v oh 0.8v batt ce out output voltage high (reset active) ns wdi pulse width 1.00 manual reset input chip-enable gating watchdog (MAX793/max794 only)
MAX793/max794/max795 3.0v/3.3v/adjustable microprocessor supervisory circuits _______________________________________________________________________________________ 5 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 -40 100 v cc -to-out on-resistance vs. temperature MAX793 toc1 temperature ( c) v cc -to-out on-resistance ( ? ) 20 -20 0 80 40 60 i out = 30ma v cc = 3.0v v cc = 3.3v v cc = 5v 160 140 120 100 80 60 40 -40 100 batt-to-out on-resistance vs. temperature MAX793 toc2 temperature ( c) batt-to-out on-resistance ( ? ) 20 -20 0 80 40 60 v batt = 3.6v v batt = 3.0v v batt = 5v i out = 250 a v cc = 0v 70 60 50 40 30 20 10 0 -40 100 v cc supply current vs. temperature (normal operating mode) MAX793 toc3 temperature ( c) v cc supply current ( a) 20 -20 0 80 40 60 MAX793/4, v cc = 3.3v max795, v cc = 3.3v MAX793/4, v cc = 5v v batt = v cc = v out max795, v cc = 5v 0.10 0.08 0.06 0.04 0.02 0 -40 100 battery supply current vs. temperature (battery-backup mode) MAX793 toc4 temperature ( c) supply current ( a) 20 -20 0 80 40 60 v cc = 0v v batt = 3.6v 100 90 80 70 60 50 40 30 20 10 0 -40 100 MAX793 lowline-to-reset threshold vs. temperature MAX793 toc7 temperature ( c) lowline-to-reset threshold (mv) 20 -20 0 80 40 60 v cc falling 250 200 150 100 50 0 -40 100 reset timeout period vs. temperature MAX793 toc5 temperature ( c) reset timeout period (ms) 20 -20 0 80 40 60 v cc rising from ov to v rst max 30 25 20 15 10 5 0 -40 100 reset comparator propagation delay vs. temperature (v cc falling) MAX793 toc6 temperature ( c) propagation delay ( s) 20 -20 0 80 40 60 10 8 6 4 2 0 -40 100 MAX793/max794 lowline comparator propagation delay vs. temperature MAX793 toc8 temperature ( c) propagation delay ( s) 20 -20 0 80 40 60 40mv overdrive v cc rising v cc falling 1.250 1.245 1.240 1.235 1.230 -40 100 MAX793/max794 pfi threshold vs. temperature MAX793 toc9 temperature ( c) pfi threshold (v) 20 -20 0 80 40 60 __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.)
MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits 6 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) 1.242 1.241 1.240 1.239 1.238 1.237 1.236 30 25 20 15 10 5 0 -40 100 max794 reset in threshold and lowline-to-reset in threshold vs. temperature temperature ( c) reset in threshold (v) lowline-to-reset in threshold (mv) 20 -20 0 80 40 60 v lowline - v rst v reset in v cc falling MAX793 toc10 2.5 2.0 1.5 1.0 0.5 0 -40 100 MAX793 batt ok threshold vs. temperature MAX793 toc11 temperature ( c) batt ok threshold (v) 20 -20 0 80 40 60 v batt falling 60 50 40 30 20 10 0 -40 100 ce in-to-ce out on-resistance vs. temperature temperature ( c) ce in-to-ce out on-resistance ( ? ) 20 -20 0 80 40 60 v cc = v rst max MAX793 toc12 1.70 1.65 1.60 1.55 1.50 -40 100 MAX793/max794 watchdog timeout period vs. temperature MAX793 toc13 temperature ( c) watchdog timeout period (sec) 20 -20 0 80 40 60 20 15 10 5 0 -40 100 MAX793/max794 battery freshness seal leakage current vs. temperature MAX793 toc14 temperature ( c) leakage current (na) 20 -20 0 80 40 60 v batt = 5.5v v cc = 0v v out = 0v 1.002 1.001 1.000 0.999 0.998 0.997 0.996 -40 100 reset threshold vs. temperature (normalized) MAX793 toc15 temperature ( c) v rst (normalized) 20 -20 0 80 40 60 v cc falling 10 8 6 4 2 0 -40 100 MAX793/max794 pfi to pfo propagation delay vs. temperature MAX793 toc16 temperature ( c) propagation delay ( s) 20 -20 0 80 40 60 v pfi falling 20mv overdrive
MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits _______________________________________________________________________________________ 7 ______________________________________________________________pin description pin supply output for cmos ram. when v cc rises above the reset threshold or above v batt , out is connected to v cc through an internal p-channel mosfet switch. when v cc falls below v sw and v batt , batt connects to out. out 1 1 reset input. connect to an external resistor divider to select the reset threshold. the reset threshold can be programmed anywhere in the v sw to 5.5v range. reset in (max794) 3 battery status output. high in normal operating mode when v batt exceeds v bok , other- wise low. v batt is checked continuously. disabled and logic low while v cc is below v sw . batt ok (MAX793) main supply input v cc 2 2 power-fail comparator output. when pfi is less than v pft or when v cc falls below v sw , pfo goes low; otherwise, pfo remains high. pfo is also used to enable the bat- tery freshness seal (see battery freshness seal , and power-fail comparator sections). pfo 7 active-high reset output. sources and sinks current. reset is the inverse of reset . reset 13 chip-enable output. ce out goes low only when ce in is low and reset is not asserted. if ce in is low when reset is asserted, ce out remains low for 10? or until ce in goes high, whichever occurs first. ce out is pulled up to out. ce out 12 6 ground gnd 6 power-fail comparator input. when pfi is less than v pft or when v cc falls below v sw , pfo goes low; otherwise, pfo remains high (see power-fail comparator section). connect to v cc if unused. pfi 4 chip-enable input. the input to the chip-enable gating circuit. connect to gnd if unused. ce in 11 5 4 watchdog output. wdo goes low if wdi remains either high or low for longer than the watchdog timeout period. wdo returns high on the next transition of wdi. wdo is a logic high for v sw < v cc < v rst , and low when v cc is below v sw . wdo 9 manual reset input. a logic low on mr asserts reset. reset remains asserted as long as mr is low and for 200ms after mr returns high. the active-low input has an internal 70? pullup current. it can be driven from a ttl- or cmos-logic line or shorted to ground with a switch. leave open if unused. mr 8 watchdog input. if wdi remains either high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and wdo goes low. wdo returns high on the next transition of wdi. connect wdo to mr to generate a reset due to a watchdog fault. wdi 10 early power-fail warning output. low when v cc falls to v lr . this output can be used to generate an nmi to provide early warning of imminent power failure. lowline 14 open-drain, active-low reset output. pulses low for 200ms when triggered, and stays low whenever v cc is below the reset threshold or when mr is a logic low. it remains low for 200ms after either v cc rises above the reset threshold, the watchdog triggers a reset ( wdo connected to mr ), or mr goes low to high. reset 15 7 backup-battery input. when v cc falls below v sw and v batt , out switches from v cc to batt. when v cc rises above the reset threshold or above v batt , out reconnects to v cc . v batt can exceed v cc . connect v cc , out, and batt together if no battery is used. batt 16 8 logic output/external bypass switch-driver output. high when out switches to batt. low when out switches to v cc . connect the base/gate of pnp/pmos transistor to batt on for i out requirements exceeding 75ma. batt on 5 3 MAX793/ max794 function name max795
MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits 8 _______________________________________________________________________________________ _______________detailed description general timing characteristics the MAX793/max794/max795 are designed for 3.3v and 3v systems, and provide a number of supervisory functions (see the selector guide on the front page). figures 1 and 2 show the typical timing relationships of the various outputs during power-up and power-down with typical v cc rise and fall times. manual reset input (MAX793/max794) many microprocessor-based products require manual- reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. on the MAX793/max794, a logic low on mr asserts reset. reset remains asserted while mr is low, and for t rp (200ms) after it returns high. during the first half of the reset time- out period (t rp ), the state of mr is ignored if pfo is exter- nally forced low to facilitate enabling the battery fresh- ness seal. mr has an internal 70? pullup current, so it can be left open if it is not used. this input can be driven with ttl- or cmos-logic levels, or with open-drain/collec- tor outputs. connect a normally open momentary switch from mr to gnd to create a manual-reset function; exter- nal debounce circuitry is not required. if mr is driven from long cables or the device is used in a noisy environ- ment, connect a 0.1? capacitor from mr to ground to provide additional noise immunity. reset outputs a microprocessor? (??) reset input starts the ? in a known state. these MAX793/max794/max795 ? supervisory circuits assert a reset to prevent code exe- cution errors during power-up, power-down, and v lowline (MAX793/max794) v reset (pulled up to v cc ) v reset (MAX793/max794) (pfo follows pfi) v ce out v batt v wdo (MAX793/max794) v bok (MAX793) max794: v reset in = v cc (v rst in / v rst ) pfo (MAX793/max794) batt on shown for v cc = 0v to 3.3v, v batt = 3.6v, ce in = gnd. typical propagation delays reflect a 40mv overdrive. 5 s v sw v cc v rst v ll t rp 25 s 25 s 25 s 25 s t rp t rp / 2 t rp / 2 figure 1. timing diagram, v cc rising
brownout conditions. reset is guaranteed to be a logic low for 0v < v cc < v rst , provided v batt is greater than 1v. without a backup battery (v batt = v cc = v out ), reset is guaranteed valid for v cc 1v. once v cc exceeds the reset threshold, an internal timer keeps reset low for the reset timeout period (t rp ); after this interval, reset becomes high imped- ance (figure 2). reset is an open-drain output, and requires a pullup resistor to v cc (figure 3). use a 4.7k ? to 1m ? pullup resistor that provides sufficient current to assure the proper logic levels to the ?. if a brownout condition occurs (v cc dips below the reset threshold), reset goes low. each time reset is asserted, it stays low for the reset timeout period. any time v cc goes below the reset threshold, the internal timer restarts. the watchdog output ( wdo ) can also be used to initi- ate a reset. see the watchdog output section. the reset output is the inverse of the reset output, and it can both source and sink current. MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits _______________________________________________________________________________________ 9 v cc v lowline (MAX793/max794) v reset (reset pulled up to v cc ) v reset (MAX793/max794) v ce out v wdo (MAX793/max794) v bok (MAX793) v pfo (MAX793/max794) shown for v cc = 3.3v to 0v, v batt = 3.6v, ce in = gnd, pfi = v cc . typical delay times reflect a 40mv overdrive v batt on max794: v reset in = v cc (v rst in / v rst ) v batt v batt 4 s v ll v rst v sw 20 s 20 s 25 s 10 s 25 s 25 s 25 s 25 s figure 2. timing diagram, v cc falling
MAX793/max794/max795 reset threshold the MAX793t/max795t are intended for 3.3v systems with a ?% power-supply tolerance and a 10% systems tolerance. except when mr is asserted, reset does not assert as long as the power supply remains above 3.15v (3.3v - 5%). reset is guaranteed to assert before the power supply falls below 3.0v (3.3v - 10%). the MAX793s/max795s are designed for 3.3v ?0% power supplies. except when mr is asserted, they are guaranteed not to assert reset as long as the supply remains above 3.0v (3.0v is just above 3.3v - 10%). reset is guaranteed to assert before the power supply falls below 2.85v (3.3v - 14%). the MAX793r/max795r are optimized to monitor 3.0v ?0% power supplies. reset does not occur until v cc falls below 2.7v (3.0v - 10%), but is guaranteed to occur before the supply falls below 2.55v (3.0v - 15%). program the max794? reset threshold with an external voltage divider to reset in. the reset-threshold toler- ance is a combination of the reset in tolerance and the tolerance of the resistors used to make the external voltage divider. calculate the reset threshold as follows: v rst = v rst in (r1 / r2 + 1) using the standard application circuit (figure 3), the reset threshold can be programmed anywhere in the range of v sw (the battery switch threshold) to 5.5v. reset is asserted when v cc falls below v sw . battery freshness seal the MAX793/max794? battery freshness seal discon- nects the backup battery from internal circuitry until it is needed. this allows an oem to ensure that the backup battery connected to batt is fresh when the final prod- uct is put to use. to enable the freshness seal, connect a battery to batt, ground pfo , bring v cc above the reset threshold, and hold it there until reset is deassert- ed following the reset timeout period, then bring v cc back down again (figure 4). once the battery fresh- ness seal is enabled (disconnecting the backup battery from the internal circuitry and anything connected to out), it remains enabled until v cc is brought above v rst . note that connecting pfo to mr does not inter- fere with battery freshness seal operation. batt ok output (MAX793) batt ok indicates the status of the backup battery. when reset is not asserted, the MAX793 checks the battery voltage continuously. if v batt is below v bok (2.0v min), batt ok goes low; otherwise, it remains pulled up to v cc . batt ok also goes low when v cc goes below v sw . watchdog input (MAX793/max794) in the MAX793/max794, the watchdog circuit monitors the ?? activity. if the ? does not toggle the watchdog input (wdi) within 1.6s, wdo goes low. the internal 1.6s timer is cleared and wdo returns high either when 3.0v/3.3v adjustable microprocessor supervisory circuits 10 ______________________________________________________________________________________ max794 reset lowline wdi ce in ce out 3.3v +5v batt reset in a0-a15 mr +5v supply failure batt on pfi 4.7k ? wdo out cmos ram address decoder 0.1 f pmos 0.1 f v cc pfo v rst = v rst in ( r1 + 1 ) gnd i/o nmi reset v cc v cc 0.1 f 3.6v r1 d s r2 (optional) si9433dy siliconix r2 figure 3. max794 standard application circuit v cc v rst v rst reset pfo (externally held at 0v) reset pulled up to v cc pfo state latched, freshness seal enabled. t rp figure 4. battery freshness seal enable timing
a reset occurs or when a transition (low-to-high or high- to-low) takes place at wdi. as long as reset is assert- ed, the timer remains cleared and does not count. as soon as reset is released or wdi changes state, the timer starts counting (figure 5). wdi can detect pulses as short as 100ns. unlike the 5v max690 family, the watchdog function cannot be disabled. watchdog output (MAX793/max794) in the MAX793/max794, wdo remains high ( wdo is pulled up to v cc ) if there is a transition or pulse at wdi during the watchdog timeout period. wdo goes low if no transition occurs at wdi during the watchdog timeout period. the watchdog function is disabled and wdo is a logic high when reset is asserted if v cc is above v sw . wdo is a logic low when v cc is below v sw . if a system reset is desired on every watchdog fault, simply diode-or connect wdo to mr (figure 6). when a watchdog fault occurs in this mode, wdo goes low, pulling mr low, which causes a reset pulse to be issued. ten microseconds after reset is asserted, the watchdog timer clears and wdo returns high. this delay results in a 10? pulse at wdo , allowing external circuitry to capture a watchdog fault indication. a con- tinuous high or low on wdi causes 200ms reset pulses to be issued every 1.6s. chip-enable signal gating internal gating of chip-enable (ce) signals prevents erro- neous data from corrupting cmos ram in the event of an undervoltage condition. the MAX793/max794/max795 use a series transmission gate from ce in to ce out during normal operation (reset not asserted), the ce transmission gate is enabled and passes all ce transi- tions. when reset is asserted, this path becomes dis- abled, preventing erroneous data from corrupting the cmos ram. the short ce propagation delay from ce in to ce out enables these ? supervisors to be used with most ?s. if ce in is low when reset asserts, ce out remains low for typically 10? to permit completion of the current write cycle. chip-enable input the ce transmission gate is disabled and ce in is high impedance (disabled mode) while reset is asserted. during a power-down sequence when v cc passes the reset threshold, the ce transmission gate disables and ce in immediately becomes high impedance if the volt- age at ce in is high. if ce in is low when reset asserts, the ce transmission gate disables at the moment ce in goes high, or 10? after reset asserts, whichever occurs first (figure 8). this permits the current write cycle to complete during power-down. MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits ______________________________________________________________________________________ 11 v cc v rst reset t wd wdo wdi wdo connected to p interrupt reset pulled up to v cc t rp figure 5. watchdog timing relationship v cc v cc reset wdo wdo 4.7k to p mr reset wdi t rp t rp t wp 10 s MAX793/max794 figure 6. generating a reset on each watchdog fault
MAX793/max794/max795 the ce transmission gate remains disabled and ce in remains high impedance (regardless of ce in activity) for the first half of the reset timeout period (t rp / 2), any time a reset is generated. while disabled, ce in is high impedance. when the ce transmission gate is enabled, the impedance of ce in appears as a 46 ? resistor in series with the load at ce out. the propagation delay through the ce transmission gate depends on v cc , the source impedance of the drive connected to ce in, and the loading on ce out (see the chip-enable propagation delay vs. ce out load capacitance graph in the typical operating characteristics ). the ce propagation delay is produc- tion tested from the 50% point on ce in to the 50% point on ce out using a 50 ? driver and 50pf of load capacitance (figure 9). for minimum propagation delay, minimize the capacitive load at ce out and use a low-output-impedance driver. chip-enable output when the ce transmission gate is enabled, the imped- ance of ce out is equivalent to a 46 ? resistor in series with the source driving ce in. in the disabled mode, the transmission gate is off and an active pullup con- nects ce out to out (figure 8). this pullup turns off when the transmission gate is enabled. early power-fail warning (MAX793/max794) critical systems often require an early warning indicat- ing that power is failing. this warning provides time for the ? to store vital data and take care of any additional ?ousekeeping?functions, before the power supply gets too far out of tolerance for the ? to operate reli- ably. the MAX793/max794 offer two methods of achieving this early warning. if access to the unregulat- ed supply is feasible, the power-fail comparator input (pfi) can be connected to the unregulated supply 3.0v/3.3v adjustable microprocessor supervisory circuits 12 ______________________________________________________________________________________ chip-enable output control ce out n p p out ce in MAX793 max794 max795 reset generator figure 7. chip-enable transmission gate v batt v cc v rst v rst v sw v rst v cc ce out reset (pulled to v cc ) ce in v batt = 3.6v reset pulled up to v cc t rp 10 s t rp / 2 v batt v sw v rst figure 8. chip-enable timing
MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits ______________________________________________________________________________________ 13 through a voltage divider, with the power-fail compara- tor output ( pfo ) providing the nmi to the ? (figure 10). if there is no easy access to the unregulated sup- ply, the lowline output can be used to generate an nmi to the ? (see lowline output section). l l o o w w l l i i n n e e output (MAX793/max794) the low-line comparator monitors v cc with a threshold voltage typically 45mv above the reset threshold (10mv of hysteresis) for the MAX793, and 15mv above reset in (4mv of hysteresis) for the max794. for normal operation (v cc above the reset threshold), lowline is pulled to v cc . use lowline to provide an nmi to the ? when power begins to fall. in most battery-operated portable systems, reserve energy in the battery provides ample time to complete the shutdown routine once the low-line warning is encountered and before reset asserts. if the system must also contend with a more rapid v cc fall time, such as when the main battery is disconnected or a high- side switch is opened during normal operation, use capacitance on the v cc line to provide time to execute the shutdown routine (figure 11). first, calculate the worst-case time required for the sys- tem to perform its shutdown routine. then, with the worst- case shutdown time, the worst-case load current, and the minimum low-line to reset threshold (v lr min), calculate the amount of capacitance required to allow the shut- down routine to complete before reset is asserted: c hold > i load x t shdn / v lr where i load is the current being drained from the capacitor, v lr is the low-line to reset threshold differ- ence (v ll - v rst ), and t shdn is the time required for the system to complete an orderly shutdown routine. power-fail comparator (MAX793/max794) the MAX793/max794? pfi input is compared to an internal reference. if pfi is less than the power-fail threshold (v pft ), pfo goes low. the power-fail com- parator is intended for use as an undervoltage detector to signal a failing power supply (figure 12). however, the comparator does not need to be dedicated to this function because it is completely separate from the rest of the circuitry. v cc gnd v cc 50pf c l * ce in *c l includes load capacitance and scope probe capacitance. 50 ? 3.6v 25 ? equivalent source impedance 50 ? 50 ? cable batt ce out MAX793 max794 max795 figure 9. ce propagation delay test circuit v cc gnd pfi to p nmi r1 unregulated supply 3.0v or 3.3v r2 pfo MAX793 max794 regulator figure 10. using the power-fail comparator to generate power-fail warning gnd v cc to p nmi c hold c hold > i load x t shdn v lr 3.0v or 3.3v lowline MAX793 max794 regulator figure 11. using lowline to provide power-fail warning to the ?
MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits 14 ______________________________________________________________________________________ the power-fail comparator turns off and pfo goes low when v cc falls below v sw on power-down. during the first half of the reset timeout period (t rp ), pfo is forced high, irrespective of v pfi . at the beginning of the sec- ond half of t rp , the power-fail comparator is enabled and pfo follows pfi. if the comparator is unused, con- nect pfi to v cc and leave pfo unconnected. pfo can be connected to mr so that a low voltage on pfi gener- ates a reset (figure 12b). in this configuration, when the monitored voltage causes pfi to fall below v pft , pfo pulls mr low, causing a reset to be asserted. reset remains asserted as long as pfo holds mr low, and for 200ms after pfo pulls mr high when the moni- tored supply is above the programmed threshold. backup-battery switchover in the event of a brownout or power failure, it may be necessary to preserve the contents of ram. with a backup battery installed at batt, the devices automati- cally switch ram to backup power when v cc falls. in order to allow the backup battery (e.g., a 3.6v lithium cell) to have a higher voltage than v cc , this family of ? supervisors (designed for 3.3v and 3v systems) does not always connect batt to out when v batt is greater than v cc . batt connects to out (through a 140 ? switch) either when v cc falls below v sw and v batt is greater than v cc , or when v cc falls below 1.75v (typ) regardless of the batt voltage. switchover at v sw ensures that battery-backup mode is entered before v out gets too close to the 2.0v mini- mum required to reliably retain data in most cmos ram, (switchover at higher v cc voltages would decrease backup-battery life). when v cc recovers, switchover is deferred either until v cc crosses v batt if v batt is below v rst , or when v cc rises above the reset threshold (v rst ) if v batt is above v rst . this power-up switchover technique prevents v cc from charging the backup battery through out when using an external transistor driven by batt on. out con- nects to v cc through a 4 ? (max) pmos power switch when v cc crosses the reset threshold (figure 13). batt on (MAX793/max794) batt on is high when out is connected to batt. although batt on can be used as a logic output to indicate the battery switchover status, it is most often used as a gate or base drive for an external pass tran- sistor for high-current applications (see driving an external switch with batt on in the applications information section). when v cc exceeds v rst on power-up, batt on sinks 3.2ma at 0.4v. in battery- backup mode, this terminal sources 100? from batt. MAX793 max794 v cc gnd pfi pfo r1 r2 v in 0v v in pfo v trip v l v pft = 1.237v v pfh = 10mv where 3.0v or 3.3v v trip = r2 + r1 1 ) ( r2 1 r1 v cc (v pft + v pfh ) v l = r2 + r1 1 ) ( r2 1 r1 v cc (v pft ) note: v trip, v l are negative v cc MAX793 max794 v cc gnd pfi pfo r1 r2 pfo v trip v h 3.0v or 3.3v v in v trip = ) ( r2 r1 + r2 v pft v h = (v pft + v pfh ) v cc v in mr (b) (a) ) ( r2 r1 + r2 figure 12. using the power-fail comparator to monitor an additional power supply: (a) v in is negative, (b) v in is positive
__________applications information these ? supervisory circuits are not short-circuit pro- tected. shorting v out to ground, excluding power-up transients such as charging a decoupling capacitor, destroys the device. decouple both v cc and batt pins to ground by placing 0.1? ceramic capacitors as close to the device as possible. driving an external switch with batt on batt on can be directly connected to the base of a pnp transistor or the gate of a pmos transistor. the pnp connection is straightforward: connect the emitter to v cc , the collector to out, and the base to batt on (figure 14a). no current-limiting resistor is required, but a resistor connecting the base of the pnp to batt on can be used to limit the current drawn from v cc , pro- longing battery life in portable equipment. if you are using a pmos transistor, however, it must be connected backwards from the traditional method. connect the gate to batt on, the drain to v cc , and the source to out (figure 14b). this method orients the body diode from v cc to out and prevents the backup battery from discharging through the fet when its gate is high. two pmos transistors in the siliconix little foot series are specified with v gs down to -2.7v. the si9433dy has a maximum 100m ? drain- source on-resistance with 2.7v of gate drive and a 2a drain-source current. the si9434dy specifies a 60m ? drain-source on-resistance with 2.7v of gate drive and a 5.1a drain-source current. using a supercap as a backup power source supercaps are capacitors with extremely high capacitance values (e.g., order of 0.47f) for their size. figure 15 shows two ways to use a supercap as a backup power source. the supercap can be connect- ed through a diode to the 3v input (figure 15a); or, if a 5v supply is also available, the supercap can be charged up to the 5v supply (figure 15b), allowing a longer backup period. since v batt can exceed v cc while v cc is above the reset threshold, there are no special precautions when using these ? supervisors with a supercap. operation without a backup power source these ? supervisors were designed for battery- backed applications. if a backup battery is not used, connect batt, out, and v cc together, or use a differ- ent ? supervisor. see the ? supervisory circuits table at the end of this data sheet. replacing the backup battery the backup power source can be removed while v cc remains valid, without danger of triggering a reset pulse, provided that batt is decoupled with a 0.1? capacitor to ground. as long as v cc stays above the reset threshold, battery-backup mode cannot be entered. MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits ______________________________________________________________________________________ 15 ce in high impedance ce out pulled to batt reset logic low batt connected to out lowline logic low reset pulled up to v cc wdo logic low wdi disabled batt ok logic low pfo logic low mr disabled, but still pulled up to v cc pfi disabled v cc disconnected from out batt on pulled up to batt out connected to batt through an internal 140 ? switch pin name status table 1. input and output status in battery-backup mode v cc 3.3v 3.6v 3.3v 3.6v v out v batt = 3.6v v rst v sw figure 13. battery switchover timing little foot is a trademark of siliconix inc. supercap is a trademark of baknor industries.
MAX793/max794/max795 adding hysteresis to the power-fail comparator (MAX793/max794) the power-fail comparator has a typical input hystere- sis of 10mv. this is sufficient for most applications where a power-supply line is being monitored through an external voltage divider (see the section monitoring an additional power supply ). if additional noise margin is desired, connect a resistor between pfo and pfi as shown in figure 16a. select the ratio of r1 and r2 such that pfi sees v pft when v in falls to its trip point (v trip ). r3 adds the additional hysteresis and should typically be more than 10 times the value of r1 or r2. the hysteresis window extends both above (v h ) and below (v l ) the original trip point (v trip ). connecting an ordinary signal diode in series with r3, as shown in figure 16b, causes the lower trip point (v l ) to coincide with the trip point without hysteresis (v trip ), so the entire hysteresis window occurs above v trip . this method provides additional noise margin without compromising the accuracy of the power-fail threshold when the monitored voltage is falling. it is useful for accurately detecting when a voltage falls past a thresh- old. the current through r1 and r2 should be at least 1? to ensure that the 25na (max over temperature) pfi input current does not shift the trip point. r3 should be larger than 82k ? so it does not load down the pfo pin. capacitor c1 is optional, and adds noise rejection. 3.0v/3.3v adjustable microprocessor supervisory circuits 16 ______________________________________________________________________________________ MAX793 max794 max795 3.0v or 3.3v to cmos ram body diode gnd MAX793 max794 max795 batt on v cc out s d g pmos fet batt on v cc out gnd (b) (a) figure 14. driving an external transistor with batt on MAX793 max794 out to static ram batt v cc gnd 1n4148 reset to p 0.47f 3.0v or 3.3v MAX793 max794 out to static ram batt v cc v cc gnd 1n4148 reset to p 0.47f 3.0v or 3.3v +5v (b) (a) v cc figure 15. using a supercap as a backup source
monitoring an additional power supply these ? supervisors can monitor either positive or negative supplies using a resistor voltage divider to pfi. pfo can be used to generate an interrupt to the ? or to cause reset to assert (figure 12). interfacing to ?s with bidirectional reset pins since the reset output is open drain, the MAX793/ max794/max795 interface easily with ?s that have bidirectional reset pins, such as the motorola 68hc11. connecting the reset output of the ? supervisor directly to the reset input of the microcontroller with a single pullup resistor allows either device to assert reset (figure 17). negative-going v cc transients these supervisors are relatively immune to short-dura- tion negative-going v cc transients (glitches) while issu- ing resets to the ? during power-up, power-down, and brownout conditions. therefore, resetting the ? when v cc experiences only small glitches is usually not rec- ommended. MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits ______________________________________________________________________________________ 17 MAX793 max794 v cc gnd 0v to p v l = r1 v pft pfi pfo r1 r2 r3 *optional c1* v in v trip v in pfo 0v v h v l r1 + r2 r2 v h = (v pft + v pfh ) (r1) v trip = v pft + r1 1 + r2 1 r3 1 r3 v cc v pft = 1.237v v pfh = 10mv where v cc gnd to p pfi pfo r1 r2 r3 *optional c1* v in r1 + r2 ) r2 v h = r1 (v pft + v pfh ) v trip = v pft ( + r1 1 + r2 1 r3 1 r3 v d v pft = 1.237v v pfh = 10mv v d = diode forward voltage drop v l = v trip where MAX793 max794 0v pfo 0v v h v in v trip (b) (a) ( ) ( ) ( ) + r1 1 + r2 1 r3 1 ( ) figure 16. adding hysteresis to the power-fail comparator: (a) symmetrical hysteresis, (b) hysteresis only on rising v in MAX793 max794 max795 v cc gnd v cc n reset generator gnd v cc reset reset p figure 17. interfacing to ?s with bidirectional reset i/o
MAX793/max794/max795 figure 18 shows maximum transient duration vs. reset- comparator overdrive, for which reset pulses are not generated. the graph was produced using negative- going v cc pulses, starting at 3.3v and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). the graph shows the maximum pulse width a negative-going v cc transient can typically have without causing a reset pulse to be issued. as the amplitude of the transient increases (i.e., goes far- ther below the reset threshold), the maximum allowable pulse width decreases. typically, a v cc transient that goes 40mv below the reset threshold and lasts for 10? or less does not cause a reset pulse to be issued. a 0.1? bypass capacitor mounted close to the v cc pin provides additional transient immunity. watchdog software considerations there is a way to help the watchdog timer monitor soft- ware execution more closely, which involves setting and resetting the watchdog input at different points in the program rather than pulsing the watchdog input high-low-high or low-high-low. this technique avoids a stuck loop, in which the watchdog timer would continue to be reset within the loop, keeping the watchdog from timing out. figure 19 shows an example of a flow dia- gram where the i/o driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. if the program should hang in any subroutine, the problem would quickly be corrected, since the i/o is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. 3.0v/3.3v adjustable microprocessor supervisory circuits 18 ______________________________________________________________________________________ 100 0 10 20 30 100 10 20 30 80 90 MAX793-fig 18 reset comparator overdrive, v rst - v cc (mv) maximum pulse duration ( s) 40 50 60 70 80 90 60 40 50 70 figure 18. maximum transient duration without causing a reset pulse vs. reset comparator overdrive figure 19. watchdog flow diagram start set wdi high return program code subroutine or program loop set wdi low
MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits ______________________________________________________________________________________ 19 ___________________chip information _________________pin configurations ce in ce out 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 batt reset lowline reset pfi (reset in) batt ok v cc out top view MAX793 max794 ce out ce in wdi wdo mr pfo gnd batt on dip / narrow so 1 2 3 4 8 7 6 5 batt gnd batt on v cc out max795 dip/so reset ( ) are for max794 transistor count: 1271 _ordering information (continued) * the MAX793/max795 offer a choice of reset threshold voltage. select the letter corresponding to the desired reset threshold volt- age range (t = 3.00v to 3.15v, s = 2.85v to 3.00v, r = 2.55v to 2.70v) and insert it into the blank to complete the part number. the max794? reset threshold is adjustable. 16 narrow so -40? to +85? max794ese 16 plastic dip 16 narrow so 16 plastic dip pin-package temp range 0? to +70? 0? to +70? -40? to +85? max794epe max794cse max794 cpe part* 8 so -40? to +85? max795_esa 8 plastic dip 8 so 8 plastic dip 0? to +70? 0? to +70? -40? to +85? max795_epa max795_csa max795 _cpa
MAX793/max794/max795 3.0v/3.3v adjustable microprocessor supervisory circuits soicn .eps package outline, .150" soic 1 1 21-0041 b rev. document control no. approval proprietary information title: top view front view max 0.010 0.069 0.019 0.157 0.010 inches 0.150 0.007 e c dim 0.014 0.004 b a1 min 0.053 a 0.19 3.80 4.00 0.25 millimeters 0.10 0.35 1.35 min 0.49 0.25 max 1.75 0.050 0.016 l 0.40 1.27 0.394 0.386 d d mindim d inches max 9.80 10.00 millimeters min max 16 ac 0.337 0.344 ab 8.75 8.55 14 0.189 0.197 aa 5.004.80 8 n ms012 n side view h 0.2440.228 5.80 6.20 e 0.050 bsc 1.27 bsc c h e e b a1 a d 0-8 l 1 variations: pdipn.eps maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .)

▲Up To Search▲

Price & Availability of MAX793

	To Download MAX793 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .